The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. Photolithography systems are used to pattern a semiconductor wafer. When semiconductor technology continues progressing to circuit layouts having smaller feature sizes, a lithography system with higher resolution is need to image an IC pattern with smaller feature sizes. An electron-beam (e-beam) system is introduced for lithography patterning processes as the electron beam has wavelengths that can be tuned to very short, resulting in very high resolution.
To enhance the imaging effect when a design pattern is transferred to a wafer, an electron proximity correction (EPC) to minimize the proximity effect is indispensable. The design pattern is adjusted to generate an image on the wafer with improved resolution. However, along with the progress of the lithography patterning, some other imaging effects are unavoidable and those imaging factors may be pattern related. Those other imaging factors are not fully considered and not effectively corrected or efficiently corrected. Therefore, it is desirable to have a system and a method for improved e-beam lithography in IC fabrication to address the above issue.